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pmarques's avatar
pmarques
Icon for New Contributor rankNew Contributor
1 month ago
Solved

EMIF HPS errors after upgrading to Quartus 25.3

So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium De...
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  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    1 month ago

    Hello,

     

    Can you check in the design for pin placement of the user reference clock? Is it placed in Bank 3A?

     

    Can you check for the pin swizzling parameter in the EMIF HPS IP?

     

     

    Regards,

    Adzim

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hello pmarques,

 

Do you have any feedback in this thread?

 

Regards,

Adzim