Rk_Athram
Occasional Contributor
Occasional ContributorDynamic Reconfiguration architecture for native phy,ATX pll with embedded streamer
Hi @CheePin_C_Intel ,
I am using stratix 10 development kit,
From transceiver user guide:
A.4.7. Embedded Streamer (Native PHY) and
A.1.4. Embedded Streamer (ATX PLL)
Shares common register...
Hi,
As I understand it, you have some inquiries related to the reconfiguration interfaces for ATX PLL and Native PHY. For your information, each of the IP has its own reconfiguration interface. Although the address value is similar i.e. 0x540 but they are two different address registers inside the device. You controller would need to connect and control them separately like case #2 in your sketch. Hope this clarify.
Please let me know if there is any concern. Thank you.
