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He4Forum's avatar
He4Forum
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3 years ago

Downtrain to PCIe Gen3x8 when generating Quartus design with Avalon-MM+ IP for S10 GX dev kit

Avalon® memory mapped Intel® Stratix® 10 Hard IP+ for PCI Express* Solutions User Guide shows that Avalon-MM+ IP can support Gen8 x 16 for PCIe. When I genetate a design with the IP, I find ...
skbeh's avatar
skbeh
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3 years ago

currentspeed_o[1:0] will indicates the link speed, i.e. Gen1, Gen2 or Gen3, see the definition in previous note.

lane_act_o[4:0] will indicates the link width, i.e. x1, ,x2, x4, x8, x16, see the definition in previous note.


In between, please check your board DIP switch SW2 setting, make sure SW2.4 is set to ON position (enable pcie x16).