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He4Forum's avatar
He4Forum
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Downtrain to PCIe Gen3x8 when generating Quartus design with Avalon-MM+ IP for S10 GX dev kit

Avalon® memory mapped Intel® Stratix® 10 Hard IP+ for PCI Express* Solutions User Guide shows that Avalon-MM+ IP can support Gen8 x 16 for PCIe. When I genetate a design with the IP, I find ...
skbeh's avatar
skbeh
Icon for Contributor rankContributor
3 years ago

Hi He Xu

Stratix 10 MX devkit OPN is 1SM21BHU2F53E1VG, while Stratix 10 GX devkit OPN is 1SG280LU2F50E2VG, both are using different device OPN.

Since you are using Stratix 10 GX devkit DK-DEV-1SGX-L-A, the AN881 example design cannot directly being used in your devkit, unless port over the pin assignments.


The design that you currently tested is generated from the 'Generate Example Design' tab as shown in screenshot below, correct?

By default this generated example design is only Gen3x8, have you modify the design to gen3x16? If no, then the link is gen3x8 only.