Forum Discussion
DE10LITE SDRAM Example code
- 3 years ago
Hello Marco,
You need to check that your RTL code is correct before you solve the timing violation.
Any changes made to the RTL code could definitely affect the timing performance due to different routing.
Also, if you require help on timing, please post a new thread as this thread has a different root cause & solution.
Thank you,
Regards,
Nurina
You may use this testbench to do RTL simulation.
I didn't add much to the testbench, instead what I did was force the signals to certain values so that it would meet the conditions to change the read and write data.
Hi Nurina,
Thank you for your time and your patience and help. at first I changed the ic and it's working. I will look at the rtl calmly to check for more problems but it is working.
Regards,
Marco