Forum Discussion
New ContributorDE10LITE SDRAM Example code
Hello Marco,
You need to check that your RTL code is correct before you solve the timing violation.
Any changes made to the RTL code could definitely affect the timing performance due to different routing.
Also, if you require help on timing, please post a new thread as this thread has a different root cause & solution.
Thank you,
Regards,
Nurina
Regular ContributorHello Marco,
The project you sent has timing violation. Before you test your project on the board, you need to ensure that the RTL functionality and timing closure is met.
Why don't you try below example project first? I have compiled it and I don't see timing violation, and I expect that RTL functionality is met so you don't have to do more debugging on here:
Can you explain how you are testing the code?
Thanks,
Nurina
Marco_GoHello Nurina,
The example from the link you sent me is the same one that I got from the cd that comes with the board, I got my functions and inserted them into the code and I don't know why it's having timing violation problems since I used the same example as the link that I used as a basis you sent me.
As I told you earlier I'm using the physical board for tests like the attached photo.
regards,
Marco
- Marco_Go
Hello Nurina,
After a new test, I did the following. I recorded the data from 0x00h to 0x0b as follows.
address 0x00h -> write value -> 0x05h -> value read -> 0xFFh ERROR !
address 0x01h -> write value -> 0x10h -> value read -> 0x10h CORRECT !
address 0x02h -> write value -> 0x20h -> value read -> 0x20h CORRECT !
address 0x03h -> write value -> 0x10h -> value read -> 0x10h CORRECT !
address 0x04h -> write value -> 0x20h -> value read -> 0x20h CORRECT !
address 0x05h -> write value -> 0xf8h -> value read -> 0xf8h CORRECT !again repeat the values in the new memory address
address 0x06h -> write value -> 0x05h -> value read -> 0x05h CORRECT !
address 0x07h -> write value -> 0x10h -> value read -> 0x10h CORRECT !
address 0x08h -> write value -> 0x20h -> value read -> 0x20h CORRECT !
address 0x09h -> write value -> 0x10h -> value read -> 0x10h CORRECT !
address 0x0ah -> write value -> 0x20h -> value read -> 0x20h CORRECT !
address 0x0bh -> write value -> 0xf8h -> value read -> 0xf8h CORRECT !see that from the address the recorded data is the same as the read data.
I don't know if timing could be causing this problem at the beginning of memory.I'm starting to think that the memory may have some physical problem.
