Forum Discussion
DE10LITE SDRAM Example code
- 3 years ago
Hello Marco,
You need to check that your RTL code is correct before you solve the timing violation.
Any changes made to the RTL code could definitely affect the timing performance due to different routing.
Also, if you require help on timing, please post a new thread as this thread has a different root cause & solution.
Thank you,
Regards,
Nurina
Hello Marco,
How did you test the code? Did you do it by simulation or signal tap?
Please send the .qar file. To generate this, go to Project>Archive Project.
Regards,
Nurina
Hello Nurina,
I'm testing the code directly on the DE10-Lite board.
I verified that the value that I write in the address 0 of the memory, is not written, even with a rewrite. The value that would be recorded at address 0 appears at address 1 and that of 1 appears at address 2. The data at address 3 is lost, which would actually be from address 2 and at address 3 the correct value appears and at 4 and 5 as well ... These reading and writing routines can be seen in the file vga_gm7123 lines 179 to 412.
I tried to comment a few lines in English to make it easier for you to understand.
I attached the file as you instructed. Thanks in advance for your support.