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CAlex's avatar
CAlex
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2 years ago

De10 standard Clock and speed issue

Hi, I'm a little confused on the clock issues, I'm working on Liunx based system with the debug mode. I created a flag signal that it will flip in 50us. I posted the signal from the FPGA to the...
CAlex's avatar
CAlex
Icon for Contributor rankContributor
2 years ago

Hi,

I'm using the terasic GHRD device tree but didn't add my IP core on that DTB file.

I just upload the .sof file to the board and test it with makefile.

The attached is the Terasic DTB file.

I hope it would be helpful.

Reguards.