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Fred_Barkins's avatar
Fred_Barkins
Icon for New Contributor rankNew Contributor
1 month ago

DE1-SoC project compiles, but board programming fails 42%. Other programs work fine

Hello, 

After successfull Quartus compilation for a relatively simple project, programming the DE1-SoC fails when reaching 42%, with the following error:

Info (209017): Device 2 contains JTAG ID code 0x02D120DD

Error (209040): Can't access JTAG chain

Error (209015): Can't configure device. Expected JTAG ID code 0x02D120DD for device 2, but found JTAG ID code 0x00000000. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf).

I manage to program it with other designs, using the same .qsf file for the DE1-SoC from Cornell's ECE5760 site.

Please see additional information in (Qsys layout, some Verilog I found relevant) at:

https://electronics.stackexchange.com/questions/764588/de1-soc-project-compiles-but-board-programming-fails-42-other-programs-work-f 

It's much more comfortable to read it there.

I've been trying to solve this issue for a very long time, any help will be much appreciated !

Fpga Devkit

2 Replies

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    As we haven't received a response to our previous notification, this thread will be transitioned to community support. We hope all your concerns have been addressed. If you have any new questions, please feel free to open a new thread to receive support from Altera technical team. Otherwise, community users will continue to assist you here. Thank you.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi Fred_Barkins,

    Thanks for the details. Since other designs program successfully, the board and USB Blaster are likely OK. This error usually happens when Quartus loses access to the JTAG chain during programming, or when the saved chain setup (.cdf) does not match what is actually detected. 


    Please try these steps:

    1. In Quartus Programmer, click Auto Detect and re-assign the .sof to the detected FPGA device (do not reuse an older .cdf).
    2. Lower the JTAG clock in Hardware Setup and retry programming.
       

    Regards,
    Fakhrul