DE0 Nios II EPCS boot

to those who got the same problem , to let you know i found the solution at least for my case ;-) here is how :

- note i was not running it not on a DE0 devp kit , but on a smaller custom devp board CycloneII

- running NiosII flash prog in debug mode from command line & adding the --debug option , i found the problem was linked to the data contents read from the EPCS chip registers

- from this error i found some tips in Altera Knowledge Base , saying it can be linked to the EPCS controller not being in the proper RESET state when trying to be accessed by the JTAG module inside the NiosII cpu

- so back into back into my QSys design i realized that the EPCS flash controller had its RESET connected to the main Clk_Reset , but not to the JTAG_Reset : so i rebuilt in QSys after having connected the EPCS controller to the JTAG_Reset of NiosII

- then i recompiled in Quartus , then on to NiosII SBT : then into Flash Programmer i selected to flash into the EPCS : 1st area the converted-SOF of the design , followed by 2nd area the converted-ELF which should include the "--after ..." option : this is VERY important to make sure you flash your NiosII-software-ELF part !AFTER! the "SOF" general fpga configuration part (produced from QuartusII) : in my case i wanted both fpga-configuration + nios2-software to be inside the EPCS flash chip , so this option was needed (read the NiosII Flash Programmer pdf guide for more details , some are really important depending on your custom board's config)

- after that all was ok :-)