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Ganesh_sf's avatar
Ganesh_sf
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2 years ago

DDR4 test failluer with BTS

Hello, The development board I'm using is the Arria 10 SOC (10AS066N3F40E2SG). We attempted to use BTS for DDR4, but we were unable to carry out a flawless test. For further clarification, please re...
Board Debug
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

I'm attaching the design here.

This design was generated in Quartus Standard version 22.1.2.

You can follow the steps from the User Guide in section 1.8 and 1.9 to run the design.

https://www.intel.com/content/www/us/en/docs/programmable/683842/21-1-19-2-0/compiling-and-programming-the-emif-design.html

There is a signal tap file that is ready to capture the signals of the DDR4 interface.

You can open Signal Tap Logic Analyzer from the Quartus's Tools tab and click on Run Analysis.

You should get similar result as picture below.

Please share your result of your test for observation.

Thanks,

Adzim

Ganesh_sf's avatar
Ganesh_sf
Icon for New Contributor rankNew Contributor
2 years ago

Thanks AdzimZM. We tested the provided DDR4 design. Traffic gen fail signal "1" was received. Please find attached the wave that was taken.

We upgraded the design and tested with Quartus Prime 22.4.

We also observe that the provided design not matches with FPGA-DDR4 configuration which is 2 GB DDR4 (256Mb x 72 x single rank) - ships with kit.