Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this (http://www.alteraforum.com/forum/showthread.php?t=32354) and there's instructive information but it's a bit old and maybe there exist other ways. I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? Thanks for your help.

I believe you want the JTAG UART core on the FPGA end and software from Altera that talks to the NIOS on the PC end. http://www.altera.com/support/kdb/solutions/rd09142004_1190.html

--- Quote Start --- I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this and there's instructive information but it's a bit old and maybe there exist other ways. --- Quote End --- In addition to the JTAG UART, those are still the only ways you can transfer data :) http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial I haven't used the JTAG UART, but I think it suffers from the same problem the other interfaces do; no easy way to access the UART from user-provided software, eg., the JTAG UART does not show up as a COM port. --- Quote Start --- I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? --- Quote End --- The problem is, that the USB interface is not a general purpose USB interface. Its a USB-Blaster and it is "owned" by Quartus and jtagd. You can access it using FTDI's D2XX DLLs directly, but I'm not sure whether that "plays nicely" if you also happen to be using Altera's tools at the same time. The Wiki tutorial contains code for accessing the JTAG-to-Avalon-MM bridge via Altera's tools, and that is pretty much the only safe way to access the board via JTAG. It would be nice if Altera would publish their jtagd protocol, as then you'd be able to write sockets code to interact with jtagd, which would in turn interact with the JTAG interface on the FPGA (in a multi-process safe manner, since all communications is via jtagd). You could just buy an FTDI C232H cable and communicate with the board via that method. Cheers, Dave

Thanks Dave. I will carefully read everything... What I wonder is if it's easy to pass data from the console to the host programs (other than Altera) or maybe I should run them in the console. Is it possible? How? And as I don't care a communication from the host to the design (only from the design to the host), can't I use a simpler way of doing it?

--- Quote Start --- What I wonder is if it's easy to pass data from the console to the host programs (other than Altera) --- Quote End --- Altera do not provide a simple method for user-coded software to interface to their USB-Blaster components, i.e., what you would like is a shared library you could call into that would play nicely with simultaneous operation of SystemConsole, SignalTap II, and other Quartus software. --- Quote Start --- or maybe I should run them in the console. Is it possible? How? And as I don't care a communication from the host to the design (only from the design to the host), can't I use a simpler way of doing it? --- Quote End --- The solutions I show in the tutorial above involve running a server in SystemConsole, and then using a TCP/IP connection from your custom code. If you do not care about running Altera's software in parallel with your code, you can use the FTDI driver to access the USB-Blaster directly. Although that involves decoding Altera's custom (and undocumented) protocols. Cheers, Dave

--- Quote Start --- (only 4 bits generated at about 10MHz) --- Quote End --- For what it's worth, you might get to your end goal faster (cheaper) by using something like FTDI UM232H module if your DE0-nano header pins aren't already used up. Configured for parallel FIFO operation, there should be ample throughput to sustain the 40Mbps you're generating. http://www.ftdichip.com/support/documents/datasheets/modules/ds_um232h.pdf http://www.digikey.com/product-detail/en/um232h/768-1103-nd/2614628

Data from FPGA to host | Altera Community

85 Replies

Altera_Forum
Honored Contributor
11 years ago
Sorry, I've typed something wrong. It's not MHz but kHz. What is the maximum data rate I can use?

I can't explain everything but I get data from another device and the design uses it to compute a 4-bit word and my computer has to use it for a software computation.

I don't use a PCIe slot because it's a laptop and I only have access to USB.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Sorry, I've typed something wrong. It's not MHz but kHz. What is the maximum data rate I can use?

--- Quote End ---

The USB-Blaster JTAG interface operates with a 6MHz clock, and it takes about 10 clocks per byte, so the maximum data rate is 600kBytes/s or 4.8Mbps.

See the performance analysis here;
https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf

Your data rate of 40kbits/s can be implemented using the JTAG interface.

The initial responses at the beginning of this thread have already provided an answer to your question. You can use the JTAG UART or the JTAG-to-Avalon-MM bridge.

Go and take a look at the DE0-nano SDRAM example in this thread;

http://www.alteraforum.com/forum/showthread.php?t=45927

The design includes a Qsys system and Tcl commands to access the board. The SystemConsole master_read_memory and master_write_memory are the most efficient commands for transferring blocks of data.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
OµµµµµµµµµµK, I'll read it next week because it's friday night there and I stop working and won't be there for the week-end. I'll let you know what I don't understand.
Altera_Forum
Honored Contributor
11 years ago
I tried the de0_nano_sdram tutotial from http://http://www.alteraforum.com/forum/showthread.php?t=45927 (http://http://www.alteraforum.com/forum/showthread.php?t=45927)
but the Quartus tcl console says:
log.txt1 KB
Altera_Forum
Honored Contributor
11 years ago
I tried the sdram tutorial first: http://http://www.alteraforum.com/forum/showthread.php?t=45927 (http://http://www.alteraforum.com/forum/showthread.php?t=45927)
but the console says:
log.txt1 KB
Altera_Forum
Honored Contributor
11 years ago
Hello,
I tried to post something but it doesn't appear, maybe because of an attached file.
So I tried the sdram tutorial on http://www.alteraforum.com/forum/showthread.php?t=45927
but my console tells:
Writing to 256 SDRAM locations
Error:invalid command name "get_service_paths"
Error: while executing
Error:"unknown_original get_service_paths master"
Error: ("eval" body line 1)
Error: invoked from within
Error:"eval unknown_original $cmd $args"
Error: (procedure "::unknown" line 7)
Error: invoked from within
Error:"get_service_paths master"
Error: (procedure "jtag_open" line 9)
Error: invoked from within
Error:"jtag_open"
Error: (procedure "jtag_write" line 7)
Error: invoked from within
Error:"jtag_write $addr $data"
Error: ("uplevel" body line 4)
Error: invoked from within
Error:"uplevel 1 $cmd"
Error: invoked from within
Error:"for {set i 0} {$i < $len} {incr i} {
Error: set addr [expr {4*$i}]
Error: set data [expr {0x12340000 + $i}]
Error: jtag_write $addr $data
Error: }"
Error: (procedure "sdram_test" line 4)
Error: invoked from within
Error:"sdram_test"

and I don't know what I should do.
Do you understand the error?
Altera_Forum
Honored Contributor
11 years ago
The moderation policy is making it impossible for me to post. I've tried the sdram tutorial but I've got tcl errors that I don't understand. I'll try...
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
The moderation policy is making it impossible for me to post. I've tried the sdram tutorial but I've got tcl errors that I don't understand. I'll try...
--- Quote End ---

You posted this text, so you could have posted your Tcl errors :)

What version of Quartus were you trying to use, and what operating system? I can re-run the script and check it works.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
I tried first to post the log as an attached file but impossible.
Then I copied the text but impossible.
So I only posted the first error.

It's version 13.1.0 on Windows 7 64-bit Enterprise edition.

Altera_Forum

Honored Contributor

11 years ago

--- Quote Start ---

I tried first to post the log as an attached file but impossible.

Then I copied the text but impossible.

So I only posted the first error.

--- Quote End ---

But you didn't post any details on the error, just that you had one, so its a bit hard to help :)

--- Quote Start ---

It's version 13.1.0 on Windows 7 64-bit Enterprise edition.

--- Quote End ---

Ok, I have 13.1 on a Win7 machine, here's a copy of the Quartus Tcl console log showing no errors;


tcl> cd {C:\Temp\de0_nano_sdram}
tcl> source scripts/synth.tcl
Synthesizing the DE0-nano 'sdram' design
----------------------------------------
 - Quartus Version 13.1.4 Build 182 03/12/2014 SJ Full Version
 - Creating the Quartus work directory
   * C:/Temp/de0_nano_sdram/qwork
 - Create the project 'de0_nano'
   * create a new de0_nano project
 - Applying constraints
 - Creating the VHDL files list
 - Generate the Qsys system
   * creating the Qsys file in the work directory
   * Tcl-to-Qsys generation for Quartus version 13.1
   * generating the Qsys system (please wait)
 - Processing the design
 - Processing completed

If you're still having trouble, just email me directly (at my forum name).

Cheers,

Dave

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Data from FPGA to host

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