CycloneIII FPGA Starter kit DDR clock pins and main oscillator voltage

Hello,

just an update to all of you reading my post.

Today I received my board and I am quite relieved as it seems working fine. So, summarizing my results:

- Using the 2.5V oscillator clocks fine the FPGA device (not really surprisingly as the bank is supplied with 2.5V); I am still wondering why Terasic is using a 3.3V oscillator on their Cyclone III FPGA Starter kit.

- Like Terasic, I connected the mem_clk pins for the DDR memory to the output pins of the PLLs;

- Modifying the mode of the PLL of the "slave" DDR controller to no-compensated removes the critical warning and saves functionality of the system. I can run my DDR memory test program (I write the whole DDR memory chips with a pattern and read it back for verification).

I hope the above is useful. If anybody has different results, please, let me know.

Michele