CycloneIII FPGA Starter kit DDR clock pins and main oscillator voltage

I decided to have CK/CKn of the DDR directly connected to the PLL output pins in my board, just like the Cyclone III FPGA starter kit board. I still have doubts but, at the end of the day, the Terasic board works fine so, at the moment, this is the safest option.

On the other side, I will use a 2.5V output oscillator at the beginning as it could be easily replaced without any pain.

In the meantime, I had the need to add another DDR chip in the design and another problem has arisen:

I tried to compile a design with 2 DDR controllers and, basically, I did something very very similar to what I found at page 17 of

"an 462: implementing multiple memory interfacing using the altmemphy megafunction": there is one clock source feeding both refclk inputs of the DDR controllers (this is a SOPC builder request), one of them is a kind of slave, has the "uses clocks from another controller" option ticked so it receives the sysclk (from the other DDR controller) on its shared_sys_clk input.

The sysclk is the clock for the rest of the system as well.

The SOPC builder is happy with this configuration and completes the generation process successfully.

When I launch the compilation process, from QuartusII I get the following :

"critical warning: pll ddr1:the_ddr1|ddr1_controller_phy:ddr1_controller_phy_inst|ddr1_phy:ddr1_phy_inst|ddr1_phy_alt_mem_phy:ddr1_phy_alt_mem_phy_inst|ddr1_phy_alt_mem_phy_clk_reset:clk|ddr1_phy_alt_mem_phy_pll:pll|altpll:altpll_component|altpll_gqg3:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "pin_ab12"

I understand this happens because, I am not feeding the "slave" DDR controller PLL (the refclk input) with the input pin it is meant to be fully compensated but I am doing it internally from the clock pin related to the other DDR controller. Am I right?

- Should I connect my external oscillator to both the FPGA pins related to the PLLs I am using and instruct QuartusII in this sense?

- Is it safe to modify the mode of the PLL of the "slave" controller to no-compensated ? (QuartusII compiles with no critical warnings in this case)

Any help is very well wellcomed.

Michele