New Contributor
New ContributorHey, were you able to make any progress on this? I seem to be having the same issue.
New ContributorYes, setting false path to RGMII-TX signals helped me to reach rx-timing. In my configuration, where tx-clk is a loop-back of rx-clk, RGMII-TX signals don't need to be constraint because the signals are driven by ddr-registers.
New ContributorThanks for the reply!
I'm not sure if that will work for me. We are generating the TX clock and delayed clock from a PLL. If I'm understanding correctly, I need to have some output delay constraints based on the 90 degree delayed clock.
New ContributorYes, you most likley need a 90° Phase shift delayed clock. The PHY I had chosen (DP83867IR) can do a 90° Shift for both RX and TX paths.
So, with that in mind, I only had to constraint the RX paths because the TX clk is driven from "0" and "1" constants, this due to ddr output registers.
