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Jodok's avatar
Jodok
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1 year ago

Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

What is best practice to reach the 500ps Data to Clock output Skew of RGMII specification v2.0 on a Cyclone V? Trying synthesizing a TSE MAC with RX-Clock to TX-Clock loopback fails because of timin...
Fpga Devkit
AshleyDoh's avatar
AshleyDoh
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6 months ago

Hey, were you able to make any progress on this? I seem to be having the same issue.

Jodok's avatar
Jodok
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6 months ago

Yes, setting false path to RGMII-TX signals helped me to reach rx-timing. In my configuration, where tx-clk is a loop-back of rx-clk, RGMII-TX signals don't need to be constraint because the signals are driven by ddr-registers.