New Contributor
New ContributorSo here is what I belive to found out so far:
Asymmetric Delays for Rx/Tx Path seem to be benefitial. I only can guess that is because the fpga can not synthesize negative delay on data trace. This I belive is because in my design the Rx-clk is looped-back as Tx-clk and can not be delayed freely.
create_clock -period 8.000 -name PHY0_RX_CLK -waveform {1.750 6.250} [get_ports PHY0_RX_CLK]
create_clock -period 8.000 -name PHY0_RX_CLK_VIRT
create_generated_clock -name PHY0_TX_CLK_VIRT -phase 100.0 -source [get_ports PHY0_RX_CLK] [get_ports PHY0_TX_CLK]
In this example both Tx and Rx have an external PHY (clk)-Delay of 2.25ns so the data at Rx will arrive in principle to soon. The fpga can now add delay to the Rx-data trace. The PHY delays the clock with 2.25ns on the Tx Path so that in general the data occure to soon. The fpga can now add delay to the Tx-data trace.
With the following constraints, a mildly ok result can be achived.
| # ************************************************************** |
| # External components |
| # ************************************************************** |
| # TVX0106 |
| set tSKQ 0.1 |
| # DP83867 |
| set TsetupT 0.55 |
| set TholdT -0.55 |
| set TsetupR 1.05 |
| set TholdR -0.8 |
| # Calculate min / max skew |
| set RxMaxDelay [expr {$TsetupT + $tSKQ}] |
| set RxMinDelay [expr {$TholdT - $tSKQ}] |
| set TxMaxDelay [expr {$TsetupR + $tSKQ}] |
| set TxMinDelay [expr {$TholdR - $tSKQ}] |
| TA Slack: | [ns] |
| Input to Register Setup | 0.244 |
| Input to Register Hold | 0.165 |
| Input to Outupt Setup | -0.045 |
| Input to Output Hold | -0.084 |
If a symmetric delay of 2ns for both Tx and Rx Path is used, the following Slack is much worse:
create_clock -period 8.000 -name PHY0_RX_CLK -waveform {2.000 6.000} [get_ports PHY0_RX_CLK]
create_clock -period 8.000 -name PHY0_RX_CLK_VIRT
create_generated_clock -name PHY0_TX_CLK_VIRT -phase 90.0 -source [get_ports PHY0_RX_CLK] [get_ports PHY0_TX_CLK]
| TA Slack: | [ns] |
| Input to Register Setup | 521 |
| Input to Register Hold | 0 |
| Input to Outupt Setup | -0.15 |
| Input to Output Hold | -0.175 |
To improove timing further I now try to manipulate D5 Delay which is impressively bad documented.
Could somebody please verify my findings.
What else can be done on that?
New ContributorHey, were you able to make any progress on this? I seem to be having the same issue.
New ContributorYes, setting false path to RGMII-TX signals helped me to reach rx-timing. In my configuration, where tx-clk is a loop-back of rx-clk, RGMII-TX signals don't need to be constraint because the signals are driven by ddr-registers.
New ContributorThanks for the reply!
I'm not sure if that will work for me. We are generating the TX clock and delayed clock from a PLL. If I'm understanding correctly, I need to have some output delay constraints based on the 90 degree delayed clock.
New ContributorYes, you most likley need a 90° Phase shift delayed clock. The PHY I had chosen (DP83867IR) can do a 90° Shift for both RX and TX paths.
So, with that in mind, I only had to constraint the RX paths because the TX clk is driven from "0" and "1" constants, this due to ddr output registers.
