Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

Hi,

May I know you're using External PHY Device with the Delay Option Is Enabled right?

Based on the AN477 page 12 design example, could you try with the 3 combinations below:

Assume trace delay, pin capacitance, and rise/fall time differences between the data and clock are negligible.

Combination 1:

tx_max_delay = tDataTrace(max) + tSU = 0ns+1.05ns = 1.05ns

tx_min_delay = tDataTrace(min) + tHold = 0ns-0.8ns = -0.8ns

Combination 2:

tx_max_delay = tDataTrace(max) + (-tSU) = 0ns+(-1.05ns) = -1.05ns

tx_min_delay = tDataTrace(min) + tHold = 0ns-0.8ns = -0.8ns

Combination 3:

tx_max_delay = tDataTrace(max) + (-tSU) = 0.33ns+(-1.05ns) = -0.72ns

tx_min_delay = tDataTrace(min) + tHold = -0.33ns-0.8ns = -1.13ns

I think Td (TS_CLK to TXD/TX_CTL output data delay) -0.85ns to +0.15ns is not related to rgmii as design example didn't include that as well.