Cyclone V: reaching RGMII Data to Clock output skew of +/- 500ps

Dear Sheng,

I am not sure if we are on the same page anymore.

My interest is to reach the timing for MII-Tx, so i am not interested in input_delay constraints.

Fact is, if I constrain tx_max_delay and tx_min_delay as following and use a PHY-Delay of 2ns, Timing Analyzer gives me negative slack.

tx_max_delay = tDataTrace(max) + tSU = 0.33ns+1.05ns = 1.38ns

tx_min_delay = tDataTrace(min) + tHold = -0.33ns-0.8ns = -1.13ns

With this constraints made, I should meet the +/- 0.5ns "data to clock output skew" spiecified in RGMII v2.0

But this is not the case, so I wonder where does this negative slack come from.

So please, is Td (TS_CLK to TXD/TX_CTL output data delay) -0.85ns to +0.15ns in Table 48 in the CycloneV Datasheet of relevance in that case? What does it mean? Other sources tell me that it should be irrelevant since the synthesis tool should best match the internal skew of the fpga.

Thank you for your response.