New Contributor
Super ContributorHi,
I think should be no problem with your ddr transmission constraint based on this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/horizontal/exm-tse-rgmii-phy.html
I think the ddr is center aligned (tPeriod/2).
(tPeriod/2 - tPHYDELAY) reflects the shifted clock edge to ensure the setup and hold times are correctly met despite the delay
New ContributorDear Sheng,
thank you for reviewing the constraint.
Indeed, tPeriod/2 represents the 90° Phase-Shift to change from edge-alinged Tx at MAC to center-alinged Rx at PHY.
Is it then so that the Quartus Synthesis-Tool is not able to fit the logic with according internal delay to fix timing without additional PHY-Delay? Is it really the Td (TX_CLK to TXD/TX_CTL output data delay) of -0.85ns ..+0.15ns that Quartus can't deal with?
I haven't fully figured it out yet, but your answers give me hope that I am close to the solution.
If you could spend a moment to have a look at the calculations I have attached to this post and could give me a quick response if the method used is reasonable, I really would appriciate it.
