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ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

cyclone v ddr3

hey to you all, im trying to interface to ddr3 component with the ddr3 uniphy controller ip . im using cyclone v soc development kit with quartus version 14.1 . i succeded to run the example d...
  • ramsoffer_123's avatar
    ramsoffer_123
    3 years ago

    hello again,

    ok i think i understands the addressing now.

    the address[29:0] uses only [29:4].(26 bits out of 30). and the 4 bits left are just padding.

    correct me if im wrong.

    thanks,

    Ram.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.