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ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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cyclone v ddr3

hey to you all, im trying to interface to ddr3 component with the ddr3 uniphy controller ip . im using cyclone v soc development kit with quartus version 14.1 . i succeded to run the example d...
  • ramsoffer_123's avatar
    ramsoffer_123
    3 years ago

    hello again,

    ok i think i understands the addressing now.

    the address[29:0] uses only [29:4].(26 bits out of 30). and the 4 bits left are just padding.

    correct me if im wrong.

    thanks,

    Ram.

ramsoffer_123's avatar
ramsoffer_123
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

hey Adzim,

thank you for the fast answer.

things are more clearly now.

still there is somthing that i dont understand.

we are using the Micron device https://media.digikey.com/pdf/Data%20Sheets/Micron%20Technology%20Inc%20PDFs/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf

according to the equation i can see that the address is 26 bits wide.

still there is a different between the address before the avalon interconnect and after the avalon interconnect as showing in the picture below.

why there is such a difference?

BR,

Ram.