Forum Discussion
Cyclone V - Differential Pair Pin Assignment 1.5V PCML fitter error
- 4 years ago
Hi Terra,
I have told you earlier, you cannot directly connect, Please design custom logic to reconstruct the word. First correct your design then try to compile.
Thank you
Kshitij Goel
So I should:
1. Instantiate SDI_II as Receiver only, Do I need to include the Protocol option?
2. Instantiate SDI_II as Transmitter only, Do I need to include the Protocol option?
3. Instantiate Intel_PLL as Fractional, 1 Output Clk, Frequency 74.25MHz.
4. Create Logic block to glue the rx_dataout[19..0] to the tx inputs: tx_datain[19..0], tx_datain_valid, tx_dataout_valid.
5. Connect the REFCLK_p0 to xcvr_refclk for the Receiver.
6. Connect the same REFCLK_p0 to the xcvr_refclk for the Transmitter.
7. Connect the PLL 74.25MHz clock to both the Receiver and the Transmitter and the Glue Logic Block.
Sound right?
Sincerely,
Terra