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vrbavojtech
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3 years ago

Cyclone V - BlockRAM read port stops working when HPS SoC added to the project

Hello, I am working on a project where I use: 1) 1-port (or 2-port) on-chip RAM (Block RAM) with data width 128b and size of 360960B, running at 160MHz. 2) A process for capturing camera data (...
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vrbavojtech
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3 years ago

Hi,

I believe I have already solved this problem. It was caused by wrong timing constraints in the SDC file for the HDMI and DCMI interfaces, I also didn't know it has to be added to the file list in Quartus otherwise it gets ignored completely by the Fitter during project compilation.

Sometimes the image glitches again, eg. when I add some VHDL signal accessed by a VHDL process serving the VGA output and also by another process sensitive to an edge of a different clock signal - I am still not sure why this interconnecting signal breaks it, so I just have to be careful about using the signals "properly". Sometimes the glitch happens even when I make minor changes to VGA-unrelated processes, also not sure why.

Thanks anyway.