Forum Discussion

MatthiasMeyer's avatar
MatthiasMeyer
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Cyclone 10 GX FPGA Development Kit - Bug in Pin Assignments

Hello, we are currently porting a processor design to the Cyclone 10 GX FPGA Development Kit. In so doing, I think we detected a bug regarding the pin assignments for the USER-LEDs in the schem...
  • Nurina's avatar
    Nurina
    3 years ago

    Hello,


    There is no bug in pin assignments. The positions of LED[0] & LED[2] are swapped on the board so this has caused confusion.

    As we know from Table 13 of the user guide, the board reference of the USER_LED sequence are as follows:

    D22: USER_LED3

    D19: USER_LED0

    D20: USER_LED1

    D21: USER_LED2

    User guide here: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-c10-gx-fpga-devl-kit.pdf


    And the pin locations corresponding to these board references are as follows:

    D22 (LED3): AC7

    D19 (LED0): AF6

    D20 (LED1): AE6

    D21 (LED2): AC6


    If you look at the board, you can see that the positions of LED2 & LED0 are swapped and the sequence are just like above.

    I hope this clarifies your confusion.


    Regards,

    Nurina


Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello Matthias,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


Regards,

Nurina