Connect inclk of PLL to output port of alt_inbuf

Generally speaking, it’s not feasible, because the structure of a regular GPIO is not sufficient to support PLL operation. This can lead to issues such as the PLL failing to lock or experiencing a delayed lock.

However, from a logic design perspective, you can try the following approach:

You can configure the GPIO pin as an input, connect it to a Clock Bridge IP, and set the output of that IP as a global signal. Then, feed this global signal into the PLL as its input clock.