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Shubhall's avatar
Shubhall
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3 years ago

Clocking Network (Quartus prime pro 20.2)

Hi, I generated low latency MAC example design from the Quartus prime pro 20.2(screenshot attached for reference - 10G_base_R_design_example.png) ; in the ATX pll IP for PHY, I did not choose any ...
Caguicla_Intel's avatar
Caguicla_Intel
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3 years ago

Hello Shubhall,


Thank you for posting in Intel Ethernet Communities.


Since your query involves Field-programmable gate array (FPGA), please be informed that this will be best answered by our FPGA support team. We will help you to move this post to the designated team for further assistance. Please feel free to contact us if you need assistance from Ethernet support team.


Best regards,

Crisselle C.

Intel® Customer Support