Contributor
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Richard Tan
ContributorHi
Following to you answer you use:
gcw__ckltchand gcw__ckltchand_1 (
.CP(i_clk),
.E(i_en),
.TE(),
.Q(gclk)
);
Is it Altera primitive code ?
Super ContributorNo, "gcw__ckltchand" is the module instantiation that you provided in your previous post. Posted on 18th April.
// Gated Clock Latch
module gcw__ckltchand (
TE,
E,
CP,
Q
);
input TE;
input E;
input CP;
output Q;
wire EN_TE;
reg CPEN;
or or1 (EN_TE,E,TE);
always @(EN_TE or CP)
if(~CP) CPEN <= EN_TE;
and an1 (Q,CPEN,CP);
endmodule //gcw__ckltchand
ContributorHi
I found the issue,
My design includes two clock gates in a row. When I remove the second clock gate, Quartus successfully convert the first clock gate.
Why does this happen? Is there any option to resolve it?
Bu the way, the message from Quartus is unclear in understanding the issue:
Reason not converted :
Found unsupported gate top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_seq_ins|block_gated_clk_seq_ins|stdc__clk_enable_nlt_reg|gcw__ckltchand|CPEN in the gated clock tree
ContributorI replaced my clock gate instance to:
gcw__ckltchand gcw__ckltchand_1 (
.CP(i_clk),
.E(i_en),
.TE(),
.Q(gclk)
);
then I re-run synthesis and get the message:
Gated clock:
top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_dig_cgu_ins|scu_top_cg_aux_clk_ins|cell__clk_enable_nlt_reg|gcw__ckltchand|an1
Base clock :
top|cnvr_pll1_inst|iopll_0|stratix10_altera_iopll_i|outclk[0]
Converted to Clock enable :
No
Reason not converted :
Found unsupported gate top|cnvr|cnvr_tlgc_inst|cnvr_scu_ins|cnvr_scu_seq_ins|block_gated_clk_seq_ins|stdc__clk_enable_nlt_reg|gcw__ckltchand|CPEN in the gated clock tree
Could you explain why Quartus did not succeed to converted?
