CII DSP kit audio examples using DSP Builder

Hi yan_w,

Thanks for having interest in my little example :)

If you want to change the audio sampling frequency, you also need to modify the frequency of dec_adc_valid signal(=en_40K).

With 40MHz system clock, generated clocks are following:

BCLK = 5 MHz (40/8)

SCLK = 2.5 MHz (40/16)

MCLK = 10 MHz (40/4) .

I set the sample rate control register of the codec as USB mode, as you mentioned, which assumes that MCLK is 12MHz. But MCLK is 10MHz in this design. Under this settings, the audio sampling frequency results in 40KHz (48KHz* 10/12). If you need a standard sampling frequency(8K, 32K, 44K, 48K, 88K, 96KHz), please feed 48MHz system clock instead of 40MHz. You may select 48MHz PLL output if you use Stratix II.

To realize 8KHz sampling in breaf:

1. Change system clock freq into 48MHz.

2. Change en_40K freq.

Line 38 of aic23_audio_clken.v should be

reg [12:0] cnt1000;

Line 44 of aic23_audio_clken.v should be

If (cnt1000 == (6000-1))

3. Modifiy sample rate control register setting.

I hope this works…