Can Instantiation components be repeated easier??

Hi,

no it's neither legal nor meaningful VHDL syntax.

You can refer to formal definition of instantiation statement in VHDL language reference IEEE Std 1076

 component_instantiation_statement ::=
   instantiation_label :
     instantiated_unit
        [ generic_map_aspect ]
        [ port_map_aspect ] ;

 instantiated_unit ::=
     [ component ] component_name
     | entity entity_name [ ( architecture_identifier ) ]
     | configuration configuration_name

U1, U2, U3 are instantiation labels, there can't be multiple lables in an instantiation.

Semantic-wise, it makes no sense to have multiple statements with identical port mapping. In this case, you are creating multiple drivers for signal Sum. Meaningful multiple instantiations will have at least some ports different.

Generate statements can however compact your code

genadders: 
for i in 1 to 3 generate 
  U : Adder 
    Port map ( 
      A => A(i), 
      B => B(i), 
      Sum => Sum(i)); 
end generate;