New Contributor
Super ContributorAll Cyclone V SoC devices are dual core, using the same Cortex A9. Where are you seeing that this particular device is single core? CPU1 has to be enabled during the boot process, so maybe you never did that.
#iwork4intel
New ContributorThank you for your quick reply. Here are the links that I found in product detail, basically these two SoC are the same but 5CSEBA5U23I7 says it has 2 processor cores while the one with S says it has 1. Also the price of these 2 are different.
https://www.intel.com/content/www/us/en/programmable/products/general/selector/product-detail.html?partNumber=5CSEBA5U23I7S
https://www.intel.com/content/www/us/en/programmable/products/general/selector/product-detail.html?partNumber=5CSEBA5U23I7
Based on the Cyclone V specification (page 12 in the following link) S indicates it is a single core version.
https://www.mouser.dk/datasheet/2/612/cv_51001-1098989.pdf
We are always using 5CSEBA5U23I7S and by reading LSB of sysmgr register (0xFFD08000) we can see cpu 1 is not available (bit set to 0) in MPU in our older 5CSEBA5U23I7S. But in our recent purchased 5CSEBA5U23I7S the bit is set to 1 meaning that CPU1 is available in MPU.
We are running exactly the same firmware image (same uboot, same linux and same FPGA) so how come only the newer FPGAs enables the CPU1 not the old ones?
