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ZhiqiangLiang's avatar
ZhiqiangLiang
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6 months ago

Avalon-MM Clock Crossing Bridge parameters setting

Hi, My FPGA model is Cyclone 10 LP 10CL120YF484. on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz. In NIOS C code, I would like to read/write registers of my IP. In my design, ...
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FOZDEMIR's avatar
FOZDEMIR
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6 months ago

Hi ZhiqiangLiang,

I have never used this IP but it looks familiar. You can find more details on Cyclone 10 IP document.

1) As far as I know, those parameters are Avalon MM Transfer parameters. They depend on your design. Data/Address/Symbol widths are your Avalon MM Transfer widths. You should choose those parameters according to your slave structure. FIFOs are for CDC purposes, so you should fill those according to your Avalon Traffic frequency. You should choose the clock domain synchronizer depth as you want (3 and above is extremely robust)

2) You will not set the parameters, but you will connect them. m0 stands for master and s0 stands for slave. Your master is NIOS and your slave is your own IP. Thus, you should connect m0 ports to related NIOS ports and s0 ports to related IP ports. (Clock, reset and Avalon MM) I think IP will do the rest, clock frequencies are not needed.

3) This IP should do the trick but you can find the min/max frequency specs of NIOS or CDC IP on Cyclone 10 IP document too.

Best regards,

FOZDEMIR