Forum Discussion

RubenPadial's avatar
RubenPadial
Icon for Contributor rankContributor
2 years ago
Solved

Arria 10 SoC Development Kit: User I/O

Hello, I'm working with Arria 10 SoC Development Kit (10AS066N3F40E2SGE2). I'm trying to use user I/0. I have noticed there are 2 MAX V CPLDs between FPGA and I/O. Following the Development Kit Use...
  • RubenPadial's avatar
    RubenPadial
    2 years ago

    Fixed. SW2.5 was used instrad of S5 by mistake. Now is working.

RubenPadial's avatar
RubenPadial
Icon for Contributor rankContributor
2 years ago

Hello again,

After compiling again it works. I don't know the reason because I have not changed any Pin configuration. I have another question related to I/0:

As I said before and using S3 (and S5) input and it is always read "0" value. According to Dev Kit Schematic there is no Pull up resistor in User I/O buttons.

I think pull up configuration must be done in MAX V CPLD. It should be done as default since Dev Kit is connected to buttons and it have no sense not to have configured pull up resitor.

Must I program MAX V CPLD to change this configuration? How I can manage this?

Thank you in advance