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MHada's avatar
MHada
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

ARRIA 10 SOC DEVELOPMENT KIT - SI ANALYSIS AND PCB LAYOUT

Dear Community, Please provide us with the SI Analysis reports of ARRIA 10. I find that missing in the folder. Like the SI Analysis report for the Cyclone V SOC Kit has been of extreme help whe...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi MHada,


The report might not be available for Arria 10 devkit.

Usually I don't see the report in the board package file for Arria 10 device.

I will try to check with the engineering if the report is available for the Arria 10 device,

Also, usually the user will do their own board simulation to get the accurate parameter setting.


The external memory interface can only be connected through the Hilo port on the board.

The medium between the memory and Hilo is the daughter card.

You can still refer to the board schematic and also pin connection guideline in the link below.


You can use the Board Skew Parameter Tool to identify the board skew.


Regards,

Adzim



  • MHada's avatar
    MHada
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi,

    Could you check with your team on the report? A gentle reminder to pass on the same to us.

    All the possible and important steps highlighted by you are being followed but still a solid reference from THE INTEL helps us so that we do not select wrong IBIS Models during simulations or at least compare the same with a reference. Besides DDR4 still remain very important for us so that we are not making mistakes in the Layout.

    Helps generate more confidence as huge amount of money is on stake while these 10 systems are getting developed.

    Thanks AdzimZM once again for your prompt replies and please excuse me for my delayed response here.