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IanD's avatar
IanD
Icon for New Contributor rankNew Contributor
3 years ago

Arria 10 hold violations

Hello, Using an Arria 10 board. Setup timing is clean, but I'm getting a few hold violations from the Arria PHY to an input FIFO. Clocks are correct and the violation only shows up sometimes. I.E -...
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Do you mean the hold violation occur sometimes? Do you get it to pass timing before?

If so, it might be marginal issue. Try to run seed sweep to get the best fit that close timing.


Do you have enough positive slack for setup? You can set "All paths" in the "Optimize Hold Timing" in the Advanced Fitter setting in the Compiler Setting.


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.