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nhadzic
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1 year ago

Apparent size limit for "User hardware1" image on Stratix 10 GX FPGA L-Tile board

I am using a Stratix 10 GX FPGA L-Tile board (DK-DEV-1SGX-L-A) and I am burning the binary image to the "User hardware1" section of the on-board flash. So far, the device utilization has been under 2...
Fpga Devkit
nhadzic's avatar
nhadzic
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1 year ago

Thank you for your response and don't worry about the delays.

Before I continue, I would like to confirm a few items:

  • I am using the Quartus Programmer to JTAG configure the FPGA and to burn POF images to the attached NOR flash. Is that what you mean by the "Flash Programmer tool"?
  • Is it possible to change the flash configuration in some way? It appears to me that the default configuration size (44,032 KB) is not sufficient to hold binary images for larger FPGA utilization rates.


I just restored my card to the factory fresh setting by using the avst.pof image from the factory_recovery folder. I will repeat my .BIN experiment now and will report the results.

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nhadzic
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1 year ago

I was finally able to perform the experiments: Sorry about the delay.

  1. I burned a known good image (FPGA is ~40% utilized). RBF for this image is 38MB. Even though I cannot use RBF, I like to use it as a proxy for the overall binary image size. This worked.
  2. I then generated binary image that contains a larger FPGA image (~52% utilized). This one is definitely larger than the allocated flash space but increased the size of the binary file so it overflows into the next flash range. This experiment did not work. Image is there as my script reads it back and compares the hash against the file we attempted to write.
  3. I then repeated step #1 to bring back the card to a working state

So it appears as if MAX-V only looks the "User HW1" location to configure an image from flash. Is there a way to increase the size of the User HW1?