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Zhilang_X_Intel's avatar
Zhilang_X_Intel
Icon for New Contributor rankNew Contributor
5 years ago

Agilex F P-tile Debug Toolkit shows no DUT listed after design loaded

Issue Description: I enabled 'Debug Toolkit' feature of P-tile AVST PCIe Hard IP in Quartus and could see the PCIe endpoint in Linux, but No DUT listed in System Console after Load Design. Tried Qu...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,


Can you try pull "p0_hip_reconfig_clk_clk" to your top level project file and assign to input clock pin as suggested by the P-tile user guide doc ?


Also ensure your Agilex dev kit board is supplying correct clocking frequency to both the reconfig_clk pins.


The other thing that you can check is to verify reconfig_reset signal if available is not stuck in reset also.


Thanks.


Regards,

dlim