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robertzab's avatar
robertzab
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9 months ago

Agilex 5 - PCIe

I have a Devkit - MK-A5E065BB32AES1. I downloaded the examples from the following link: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-modular.html I...
Board Debug
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
9 months ago

Hi Robert,

I try to download the from the same link as yours and run full compilation in Quartus v24.3.1.

the compilation PASS 100 % without any error.

Another method you may try is to generate from our IP catalog, you may refer the step in 2.2. Generating the Design Example

  • I try to compile the same in IP catalog, the result was passing as well, attach the design .qar file as per your reference purpose

Regards,
Wincent_Altera



robertzab's avatar
robertzab
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8 months ago

Hi,

Thank you for your response.

I downloaded your project and ran it on my device.

I connected the Dev-Kit to the motherboard, uploaded the program, but unfortunately, Windows does not detect any device – the same issue occurs on Linux, no device is detected.

I also have a devkit from Arrow (Arrow AXE5-Eagle FPGA Dev Kit). Using the same project – only changing the pin assignments – Windows detected the connected device, and so did Linux.

According to the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express Design Example User Guide), I installed the driver:

 

I ran the test program: ./software/user/example – and got the following results:

 

Even when performing individual read and write operations, the result is the same.

From the Ubuntu side, I checked:

robert@robert-Z590:~$ lspci -d 1172:
02:00.0 Unassigned class [ff00]: Altera Corporation Device 0000 (rev 01)

LnkCap:	Port #1, Speed 8GT/s, Width x4, ASPM L0s L1, Exit Latency L0s unlimited, L1 unlimited
		ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
		
LnkSta:	Speed 8GT/s (ok), Width x4 (ok)
		TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-

 

So the link between the device and the computer exists – but there is still a problem with reading and writing.

I checked the signal assignments according to the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express User Guide) – all pins match the values from the table.

 

I enabled the debug toolkit and got the following results:

Do you have any idea where the issue or error might be? 

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    8 months ago

    Hi Robert,

    It seen unusual to me that from your lspci command, it seen like the speed and width is in expected way.
    However, the debug toolkit show it stuck at recovery_rcvrlock.. Is this happen during the transition or before the transition ?
    Can you please try to redo the equalization ?

    I suggest to capture a signalTAP to have a better view.
    https://community.intel.com/t5/FPGA-Intellectual-Property/How-to-run-PCIe-Gen-5-Design-Example-using-Altera-FPGA-device/td-p/1640988

    Perhaps, you can try to refer the document under Appendix C, D and E. (in case you missing any step)
    Although it is targeted Agilex 7 but overall step will be the same.

    Regards,
    Wincent_Altera

  • SandorD's avatar
    SandorD
    Icon for New Contributor rankNew Contributor
    5 months ago

    Hi @robertzab , apologies for the the appearance of freeloading but...

    You said, "I also have a devkit from Arrow (Arrow AXE5-Eagle FPGA Dev Kit. Using the same project – only changing the pin assignments – Windows detected the connected device, and so did Linux."

    I have the same kit and also attempted to do the same (TEI0185-03 rev). Unfortunately, that board is connected up to a different bank for PCIe compared to the Intel Dev Kit and the clocking architecture is also different. After much experimentation with different versions of Quartus PRO (up to 25.1) and playing with the pin outs, modifying the pcie_ed example and building up a simple PCIe design from scratch etc., I can now compile the design cleanly and program the board but the PCIe just stays in reset.

    I also have access to an Intel Modular Dev Kit (which works, although, the ES series board has some issues with the PCIe lane connectivity which makes <4x configs not to work) but it seems like a waste not to use the AXE5-Eagle so I'm keen to get it going. PCIe is a must have for my project. It's of some concern that as far as I can tell, there are no PCIe example designs published for the AXE5-Eagle, even after quite a bit of time and with PCIe being one of its core features (it even has the edge connector) - I thought it may be a sign of problems.

    Anyway, if you (or anybody) didn't mind sharing some details of how you got PCIe working on the AXE5-Eagle, it would be greatly appreciated!

    Thanks,
    Sandor

  • kocis's avatar
    kocis
    Icon for New Contributor rankNew Contributor
    4 months ago

    Hi robertzab,

    I also have the same board Arrow AXE5-Eagle (Rev-3).

    I tried to follow the documentation (GTS AXI Streaming Intel® FPGA IP for PCI Express Design Example User Guide) along with the board schematics but I cannot get it to work. I am getting an invalid assignment error for the pin PIN_AY120.

    Can you share your constraints with me? It seems like I am missing something.
    Thanks in advance.

    Best regards,
    Kocis