Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera

Hi,

This is regarding the clock tree used in the Agilex 7 FPGA M-Series Development Kit. I have a few questions and would appreciate your clarification.

1. Why is the 390.625 MHz SyncE clock generated by the Si5518 (U92) provided to the Si5395 (U14) and subsequently routed through the Si5391 devices to the DDR5 and HBM reference clock pins of the Agilex M FPGA?

2. Why is the output of Si5391 (U35) connected to an input of another Si5391 (U93), and similarly, why is an output of U93 connected back to an input of U35? What is the purpose of these interconnections?

3. Why is the 312.5 MHz LVDS SAMPLE clock output from the Si5518 connected to the ToD block of the Agilex M FPGA? What function does this signal serve in the ToD block?

4. In the Si5518, why is the PPS output looped back to one of the PLL inputs (1PPSFB)? What is the purpose of this feedback connection in the schematic?

5. Similar loopback connections are also observed in Bank 13C of the Agilex M FPGA. Why is this loopback connection required ?

I would appreciate your response to these queries. Any pointers to relevant documentation or application notes would also be very helpful

Regards,

Thulasi