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HungLam's avatar
HungLam
Icon for New Contributor rankNew Contributor
6 years ago

A10 GX DEV KIT - PCIE to control SPI core ( 3 wire) IP - Regmap

Hi, I am designing an application similar to PCIe to SPI bridge. I used PCIe HIP and SPI ( 3 wire) peripheral. My design used only bar0 and bar4, and I connect bar4 avmm to spi core avms, PCIe bar4...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

There is no specify the MAX clock, but you probably can try to simplify the design by connecting with JTAG MASTER (using system console) or NIOS processor instead of PCIe to debug it. It allows you to easily run with different clock rates. After the simple one is working, then you can change it back to use PCIe and then understand the difference. You might also need to capture signaltap to confirm if all the registers are written correctly.

Regards -SK