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DAVID455912142's avatar
DAVID455912142
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1 year ago

Why does my cyclone V GX pcie fail to establish communication when the temperature is low?

We are establishing connections and communication between the PCIe IP core of CYCLONE V GX FPGA and the CPU daughter card. The chip model is 5CGXF7C6F23I. We conducted experiments by heating the FPG...
VenT_Altera's avatar
VenT_Altera
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1 year ago

Hi DAVID455912142,


Thanks for reaching out.


Please address the following questions:

1. Are you using PCIe design from our FPGA Design Store? If yes, what is the design example?

2. Besides, does the PCIe link-up succeed only at room temperature?

3. What version of Quartus are you using?

4. Full device OPN of the FPGA


Could you please try the workaround in the below KDB? Note that the devices affected by this issue are Cyclone V GT and ST devices.

https://www.intel.com/content/www/us/en/support/programmable/articles/000077431.html


Thanks.

Best Regards,

Ven



DAVID455912142's avatar
DAVID455912142
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1 year ago

Hi ven

1. We did not directly use examples from the FPGA store.We used the NIOS II to access the PCIe IP hard core and communicate with the CPU card.

See the attachment for the environment。

2.This time,out of 50 pieces,43 pieces can establish communication at room temperature,while 7 pieces cannot communicate normally at room temperature.These 7 pieces require the FPGA chips to be powered on and work for 3-4 minutes to heat up,after which a restart can establish communication."

3.Quartus14.1!

4.We are currently communicating with our distributor regarding the order number

Thanks.

Best Regards,

david