using HLS to generate a simple non-stalling feedforward pipeline with a deterministic latency

Sorry the late response. I was able to get in contact with some Intel HLS developers that helped me with configuring the design.

The source of the latency indeterminism had something to do with the S10 HyperFlex pipeline register optimizations. Since my constraints were more latency sensitive than frequency sensitive, they suggested I turn the optimization off which generated the simple feedforward pipeline I expected; at least as far as I could tell through repeated simulation runs. (Turn off "hyper-optimized-handshaking".)

It is important to note that for this to work, I did write the code in such a way that I expected the result to be stall-free and feedforward. I learned that the attributes do not do anything to help generate such a design; they just modify the interface which helps if the design already is stall-free. As noted in the original question, the only stall was in the input interface which we discovered was caused by those S10 optimizations.