The IO standard for mipi transmission using general-purpose IO

Thanks for your answer. the specific OPN is EP4CE6F17. And can you see the hardware design this time? I use bank3 for mipi design(R4 & T4 as differential pair for HS clk, N5 & N6 as single end for LP clk, R5 & T5 for HS data lane0, M7 & K8 as single end for LP data lane0, R7 & T7 for HS data lane1, R6 & T6 for LP data lane1, R3 & T3 for HS data lane2, N3 & P3 for LP data lane2, R8 & T8 for HS data lane3, N8 & P8 for LP data lane3, as shown in the image below). in my opinions, these pins need to design as inout type to do state switch between HS and LP. And there are two questions when I design my qurtus project.

1. R4 & T4 do not support bidirection(only output) when I choose differential 1.8-V HSTL IO standard in my pin planner, so I have to choose 1.8-V HSTL CLASS I IO standard.
2. all HS data lanes I list above do not have differential 1.8-V HSTL IO standard in the pin planner, so I have to choose 1.8-V HSTL CLASS I IO standard.

It compiled successfully, but I think it is not satisfied with the requirement in AN754. Could you give me some suggestions about my questions? Is there something wrong in my understanding?