Forum Discussion
NurAida_A_Intel
Frequent Contributor
5 years agoRE-copy from email to Forum for tracking purpose :
Dear Samson,
Sorry for the long wait.
From what I discussed with my colleague, please refer to comments below:
1.Reference Design ( from AN 888) :
- Firstly, we need to know whether this is IP problem or user traffic problem.
- Hence, please run the ref design. Yes, the ref design use NIOS is true. And it differs from what you are doing. I acknowledge that. But you can proceed to run it regardless use nios or not and check if the waitrequest signal stuck or behave as expected. The reason behind is from the ref design, you can observe how the Nios control the PHYLite and get the idea on how it works so that you are able to do the same on your side. Most importantly, this is the way to isolate whether the failure is due to IP issue or user traffic issue.
2. Signal Tap:
- Have you tried to run using signal tap on the Stratix 10 design, see if there is any anomaly? I checked the design (IO_Library.qar), but I can’t see any Signal Tap file.
3.Avl_clk:
- The waitrequest signal comes from Nios and Nios is driven by avl_clk. You may want to re-check if avl_clk is correctly connected to PHYLite IP.
4. I/O Column:
- Does the EMIF IP and PHYLite IP located in the same IO column? I recall there was issue with EMIF IP in the same column.
- Both the local_cal_fail signal and the local_cal_success signal may not assert high after EMIF calibration when both EMIF IP and an PHYLite IP with dynamic reconfiguration enabled are placed in the same I/O column.
Regards,
Aida
- KQ1 year ago
New Contributor
Hi, everyone. Can EMIF and PHYlite IP share the same IO ? I use PHYlite ip to do pin placement, it works , but failed wihle implementing . It seems there are some constriants.