Forum Discussion

LHinC1's avatar
LHinC1
Icon for New Contributor rankNew Contributor
6 years ago

Stratix 10 PHY Lite Avalon bus waitrequest issue

Hi everybody , we used Arria 10 FPGA with PHY Lite in our last design. In our new design , we migrate to Stratix 10 and we use PHY Lite to interface DDR4 DRAM. The architecture of Arria 10 PHY Lite i...
NurAida_A_Intel's avatar
NurAida_A_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi Sir,

Please accept my apology for the delay in response due to workload.

Can you please help to verify following ?

1. Ensure reset_n is toggle out of reset mode. From 0 to 1

2. Ensure correct clock frequency is supplied to DDR4 pll_refclk input pin. This will enable DDR4 PLL to operate and generate all desired output clk to DDR4 IP

3. Ensure the pll_locked and interface_locked is high. Data transfer should start after the assertion of this signal.

Regards,

Aida

  • LHinC1's avatar
    LHinC1
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi Aida ,

    Thank you for your reply ,

    1. we are sure that the reset_n is at 1 , we checked it on signal tap.

    Our interface clock frequency is 1200MHz , and we select 150MHz for the PLL reference frequency.

    We measured the input clock frequency and we are sure that it is 150MHz.

    And I measured the clock output frequency , it is exactly 1200MHz.

    We used Arria 10 PHY Lite in our last project , I believe that we should have set the PHY Lite settings correctly.

    Other than clock signal output , we already have the control , address , DQ , DQS signals correctly output ,

    thus our next step is to control the timing , however we don't know why the waitrequest signal of the avalon bus is always high ,

    and we failed to access the avalon bus information.

    3. Yes , we checked the pll_locked as well , it is 1 after the reset_n goes high.

    We are currently using a 50MHz clock on the avl_clk , according to the specification , maximum frequency of avl_clk allowed is 167MHz , is it right ?

    Looking forward to hearing from you , please let us know the possible reasons of having the waitrequest signal tied high.

    Thanks ,

    Samson