Forum Discussion
New ContributorSignalTap influences the designed timing?
Thanks for your feedback,
As mention previously, you have to treat signaltap as any logic inside the fpga. Which means adding a signal tap equivalent to add extra custom logic to your design.
Sometimes, add additional logic will lead to timing closure and vice versa. If you need help for us to dive into it. You may have to send us a design.qar to look into it.
Another way to close this type of timing is use DSE. https://www.youtube.com/watch?v=1cc74E3zaeI since you have a design with timing close before.
Super ContributorYou may have to treat signaltap as any logic inside the fpga for that is what it is.
The timing must not be violated after removing the signal tap or else your output would be unreliable.
Usually, signal tap will add more logic towards it and removing will ease the timing. You may have to analyze your design again.
New ContributorThanks for reply.
I haved analyzed my design and found something else. I implemented TDC on Cyclone IV, the designed carry chain is enough long for clock period, logically by timing report, the setup time for some registers will be not met. The problem is, when i compile with SignalTap, the setup time reported in worst-case given by the Timequest Timing Analyzer is about 'altera_reserved_tck' and no other warnings or errors, this 'altera_reserved_tck' comes from JTAG, if i'm correct, but it's not the desired timing report about my design. (ps:without SignalTap the timing report is correct)
So, is there any way to get the wanted timing report from full compilation with SignalTap?
Another question is, is that correct that the delay for odd-indexed delay cell is enormously larger than the even-indexed delay cell? For example, the delay for first cell is much larger than the second one.
Best Regards
