Sample project with RTL module library not working

i++ component_testbench.cpp expHBU.a -v --dont-error-if-large-area-est -march=Cyclone10GX -o test-fpga
Target FPGA part name: 10CX220YF780I5G
Target FPGA family name: Cyclone10GX
Target FPGA speed grade: -5
Resolved expHBU.a to /home/grads/messn036/OpenCL-HUBERT/OpenCL-HUBERT/component_ip/expHBU.a
Analyzing component_testbench.cpp for testbench generation
Creating x86-64 testbench
Analyzing component_testbench.cpp for hardware generation
Verifying version information in the included files.
Expecting version 21.2.0.67.4 for all included files.
Included files passed version check. Checked: /home/grads/messn036/OpenCL-HUBERT/OpenCL-HUBERT/component_ip/expHBU.a
Preprocessing FPGA Libraries
Optimizing component(s) and generating Verilog files
component_testbench.cpp:9: Compiler Error: undefined reference to 'expHBU(unsigned char)'
HLS Main Optimizer FAILED.
make: *** [test-fpga] Error 1

I have done some basic troubleshooting in the meantime an narrowed down my error a bit. To compile the RTL library, I am using the following commands

fpga_crossgen exp_wrapper.xml --target hls --emulation_model expHBU.cpp -o expHBU.o
fpga_libtool --target hls --create expHBU.a expHBU.o

But It seems like I need to use different flags to get the xml and verilog to compile for NOT the x86-64 simulation but for the test-fpga version. Am I right here? When should I expect to compile the xml and verilog?