Forum Discussion
The 2nd link doesn't have a solution. The 1st link is vague. I don't know which output signals need to be assigned to zero value but I am looking into it. However, it is better for Intel Altera let me know in details how to modify the Modelsim simulation. I would like to restate my issue again after a few re-installations so we can understand the issue accurately
"The Modelsim simulation which is generated by HLS Quartus standard 19.1 Windows 10 virtualbox for the Intel-provided counter cpp example cannot be simulated from ModelSim/vsim software. After `do tb/sim/mentor/msim_run.tcl`, ModelSim can set up and start the simulation. However, after around 12ns in simulation, the ModelSim will crash and throw an error 'Trouble with Simulation Kernel'. If running the simulation by executing hls bin file, test-fpga.exe, the counter can increment correctly up to 100 counts."
I tried with Quartus 21.1 on windows and centos7.5 as well. I see the same problem happens to Quartus Pro 21.1 on Windows 10 virtualbox but it works correctly for centos7.5 vm
I ran the simulation to check the state of signals. From the screenshot, all the signals related to the counter instance are set specific values. Let me know if anything else I can check.