Reproducing the same results in Quartus

Intel OpenCL compilation flow includes several attempts to improve kernel clock frequency in post_flow.tcl calling the PLL frequency adjustment script: source "$sdk_root/ip/board/bsp/adjust_plls.tcl". Running this script may result in different PLL settings depending on primarily utilizaiton of FPGA and speedgrade. If nothing has changed in your compiles including your CPU, this is indeed strange result. But in general, you may have different number of workgroups or compute units in FPGA. As the utilization of FPGA grows the maximum frequency tends to go down which may explain the different multiply and divide ratio. If your applicaition requires a fixed repeatable frequency it is quite easy to change the script to your local copy which does only one attempt. BTW this will save you some compile time too.