Questions about 10GE mac configuration and CRC inserting enabling in eth_e2e_e10

Hi JohnT,

Thanks for your feedback and support.

I think your suggestion is a possible way I have interest to follow.

I have check the userguide of low latency 10G MAC and found

CRC checksum automatically inserting to stream in the frame can be enable or disable by the register tx_crc_control,which is in the offset 0x0026 of TX configuration and states register.

Unfortunately ,I have not found any specific SV OR V code to write or read CSR of MAC in the hardware code under the location \..\examples\eth_e2e_e10\hw\

I guess that part is done by CPU side through the CCIP, that is why I have not seen the specific CSR configuration value and check them.

I would like to check these 10GE MAC CSR value in these design example ,so I could know how the MAC being configured and worked, which can be used to explain several questions like

1,where the missing four bytes from wireshark ? if the last 4 crc-check sum, generated by the user code, is being treated as part of payload ,and on top of that, MAC IP still insert another extra crc checksum into the end of stream probably, then the last 4 bytes crc value might not be able to see on wireshrk.

CRC probably being computing twice I guess lie below, once is done by the user design code CRC32_gen, and another CRC check sum is automatically add into the stram and invisible to user .I need csr VALUE to confirm this .

Thanks

Jim