Power analysis flow for OpenCL designs in FPGA devcloud

The Intel PAC A10 board is based on Bittware's A10 board and is apparently compatible with Bittware's monitoring tool which reports board voltage and power data among other things. A couple of years ago I developed a function to read the power sensor in the host code for Bittware's A10 board through Bittware's provided API. You can find the function here:

https://github.com/fpga-opencl-benchmarks/rodinia_fpga/blob/master/common/power_fpga.h

Assuming that Bittware's toolkit is installed on Devcloud and the board is connected to the host machine via USB, you might be able to use that function as it is or with some modifications to read the full power of the board during kernel execution.

The OpenCL flow has completely changed starting from v19.1 and the old method of running quartus_pow on the project file probably doesn't work anymore, nor does that method provide accurate power usage anyway unless it is coupled with signal activity data.